Introduction: Carrier board design is the key to SoM success

Although the SoM provides the “brain”, the “body” and the “senses” are determined by the carrier board. A well-designed carrier board is the prerequisite for the SoM to fully function and operate stably. This article takes the ECK20-6Y28C as an example and explains the key points of carrier board design in detail.
II. Power system design

Power input: The ECK20-6Y28C is powered by a single +5V ±10% supply, and a supply current of about 0.5 A is recommended. A DC-DC or LDO solution can be selected, but note that the power margin of the DC-DC should not be too large so as not to affect ripple; for the LDO, attention should be paid to heat dissipation.
Power domains and timing: The internal power-on sequence of the core board is SNVS → NVCC → VBUS. When designing the carrier board, it is necessary to ensure that the power rails of external circuits (such as CAN transceivers) match the I/O power domains of the core board, to avoid abnormal signals or device damage caused by inconsistent power-on timing.
Backup power: The VBAT pin (J1-42) can be connected to an external RTC battery with a voltage range of 2.6 V to 3.3 V. However, please note that NXP recommends using an external RTC circuit, because the internal RTC has high power consumption, which shortens the battery life.

III. Key interface layout suggestions

LCD interface: The LCD signals on the core board have already been length-matched and controlled to 50-ohm impedance. On the carrier board, it is recommended to route traces with equal length (error within ±100 mil), spacing ≥ 2W, and place the series matching resistors close to the BTB connector.
uSDHC card interface: The clock signal is already in series with a 10-ohm matching resistor. On the carrier board, it is recommended to route traces with equal length (error within ±100 mil), spacing ≥ 2W, and follow the 3W rule for the clock signal.
USB interface: Control the differential impedance to 90 ohms, keep signal lines as short as possible, and perform equal-length routing.
Ethernet interface: There is no PHY on the core board, so a PHY chip must be designed on the carrier board. The RMII signal equal-length error is within ±100 mil, the differential pair internal error is within ±30 mil, and the network transformer should be placed close to the PHY (within 20 mm).

IV. I2C and CAN interface considerations

I2C: The core board does not provide pull-up resistors, so a pair of 2.2K to 10K pull-up resistors must be added to each bus on the carrier board. Check for device address conflicts and ensure the interface level is 3.3 V.
CAN: Communication works by simply adding an external CAN transceiver (such as the SN65HVD230). Note: the transceiver power rail should be consistent with the I/O level of the core board, to avoid connecting 3.3 V signals to a 5 V-powered transceiver, which may cause damage.

V. Hardware design checklist

Power rail consistency: check whether the levels of all I/O signals match.
ESD protection: add ESD protection devices to external interfaces (such as USB and Ethernet).
High-speed signal equal-length: high-speed signals such as USB, Ethernet, SDIO and display all require equal-length control.

Summary

The power design, interface layout and signal integrity of the carrier board are the key to the stable operation of the SoM system. Strictly following the manual recommendations can effectively avoid common design pitfalls.